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Cypress Semiconductor /psoc63 /BLE /BLESS /EFUSE_TIM_CTRL3

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Interpret as EFUSE_TIM_CTRL3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PGM_SCLK_SETUP_TIME 0PGM_SCLK_HOLD_TIME 0AVDD_CS_SETUP_TIME 0AVDD_CS_HOLD_TIME

Description

EFUSE timing control Register (for Program)

Fields

PGM_SCLK_SETUP_TIME

PGM to SCLK setup time (TS_PGM) PGM_SCLK_SETUP_TIME <CS_SCLK_SETUP_TIME
PGM_SCLK_HOLD_TIME

PGM to SCLK hold time (TH_PGM)
AVDD_CS_SETUP_TIME

AVDD to CS setup time into program mode (TSP_AVDD_CS)
AVDD_CS_HOLD_TIME

AVDD to CS hold time out of program mode (THP_AVDD_CS)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data